1. Field of the Invention
This invention relates to an emitter coupled logic circuit, and is applicable to shift registers and frequency dividers, for example.
2. Description of the Related Art
Nowadays, it is becoming more common to set a signal processing mode based on various control data output as serial data from a microprocessor in signal processing integrated circuits (hereinafter referred to as signal processing IC) for processing analog signals as well.
In the case of a car-mounted stereo system, for example, sound is usually reproduced under control with touch-pad input keys and according to setup information selected by a user through the user's setting of a sound volume, balance in the sound volume between the right-hand and left-hand speakers, and various functions, such as a tone control and a fader, by using serial data.
On this occasion, shift registers for receiving serial data, latch aided serial-to-parallel conversion, data retention, etc. are indispensable for performing these functions, and their logic circuits are normally composed of emitter coupled logic circuits (hereinafter called ECL circuits), integrated injection logic (IIL) circuits, and so forth.
For example, a conventional shift register can be composed of a cascade connection of two flip-flops, FF1 and FF2, as shown in FIG. 1, such a shift register is disadvantageous in that many elements constitute a stage, and that the circuit scale is rather large when connecting a shift register of two or more stages.
As this reason, the flip-flops FF1 and FF2 are basically composed of transfer gates 2 and 12 consisting of two differential pairs of transistors Q1, Q2 and Q11, Q12, and latch gates 3 and 13 consisting of load resistors R1, R2 and R11, R12, and transistors Q3, Q4 and Q13, Q14.
The operational states of the transfer gates 2 and 12 and the latch gates 3 and 13 are switched by switching gates 4 and 14 consisting, respectively, of one differential pair of transistors Q5 and Q6, and the other differential pair of transistors Q15 and Q16.
Also, the switching gate 4 and 14 are connected to reset gates 5 and 15 and current sources 6 and 16.
If the reset signal RST is a logic level "L", since a transistor Q7 becomes "ON", the reset gate 5 controls the switching circuit 4 to remain "ON" by leading current from the common emitters of the transistors Q5 and Q6, via the transistor Q7.
If the reset signal RST is a logic level "H", since a transistor Q8 becomes "ON", the reset gate 5 forcibly turns the potential of the connection midpoint QM to logic level "L" by leading current from the connection midpoint QM of the load resistor R1 and the transistor Q3 via the transistor Q8 of the reset gate 5.
However, if a shift register is composed of cascade connection such flip-flops FF1 and FF2, it is necessary to arrange about 24 elements a stage, as shown in FIG. 1. Thus, to constitute a shift register of 50 stages, no fewer than 1200 elements are required, resulting in a very large circuit scale, as evident from FIG. 1.
Similarly, among ECL circuits of this related art equipped with transfer gates and latch gates, the one shown in FIG. 2 is widely known. And in this case the need to arrange a large number of elements per a stage also causes a disadvantage in that a very large circuit scale is required for constituting a multistage frequency divider.
That is, in the case of the frequency divider 20, changing operational states is effected by alternately switching through switching gate 23 the currents to be led from the latch gate 21 and transfer gate 22, latch gate 31 and transfer gate 32 into the current sources 24 and 34 respectively.
The frequency-divided output of the clock pulse signal CP, from output terminals Q and Q of the output stage 25 undergoes polarity inversion in transferring the state of one gate to another or retransferring the state of one gate to another.
However, in a case constituting a frequency divider like this, about 26 elements are required in a stage as evident from FIG. 2, and still more elements are required to constituting a multistage frequency divider. As a result a problem arises in that circuit scale becomes very large.